As is well known, transistors in semiconductor devices are commonly constructed on silicon wafers using a chemical vapor deposition (CVD) process along with many other process steps. Individual transistor components are fabricated on a wafer using CVD to deposit materials on the wafer that will eventually be etched to define source, drain or gate regions of a transistor. Components are formed over either n-tub or p-tub regions in the silicon substrate. The individual transistor regions are then doped with either an n-type or p-type dopant according to the desired type of semiconductor device.
In p-channel metal oxide semiconductor (PMOS) devices, boron is typically the p+dopant that is implanted into the source/drain regions. However, during this phase of the manufacturing step, heavily doped boron in the polysilicon gate has a tendency to diffuse through the gate oxide layer and into the p-channel areas of the device. This diffusion often leads to severe threshold voltage instablilities and reliability problems in the PMOS device.
One solution to counter the effects of the boron diffusion is to use an oxide-nitride-oxide (ONO) or oxide-nitride (ON) gate dielectric process to prevent boron diffusion. During the ONO or One process, multiple layers of dielectric are processed in separate furnaces and furnace cycles to create a boron diffusion barrier between the p+ doped areas and the p-channel areas of the device. While ONO or ON is an effective solution to boron diffusion, it is a costly process with low throughput. More importantly, ONO or ON dielectrics have severe interface trap problems that cause numerous trap induced device problems, such as short channel effects and transistor instability issues.
Accordingly, what is needed in the art is a single step process to form a very thin nitride layer over the gate dielectric to reduce the diffusion of boron from p+ doped poly or amorphous silicon into p-channel areas of the device without interface trap and mobility problems.